Comparing Propagation Delays and Power Dissipation on CMOS-simulated Circuits in HSPICE

نویسندگان

  • Tsung-Han Sher
  • Shermin Arab
چکیده

A four-bit adder is simulated using HSPICE in two classic design methods: a ripple-carry adder (RCA) and a carry-look-ahead adder (CLA). All components of the adders are composed of PMOS, NMOS, and capacitors. The propagation delay and power dissipation were measured under different VDD values and different operating temperatures in HSPICE. A comparison of these two metrics were analyzed between the RCA and CLA, and concludes that both the CLA and RCA operates optimally at low temperatures and are unsuitable for high VDD environments, CLA is preferred for faster computation while RCA is preferred for smaller chip size, and the CLA is preferred for high-frequency adder usage situations, and the CLA is more suitable for low-VDD systems.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Deep Submicron Switching Current Modeling for Cmos Logic Output Transition Time Determination

Non zero signal rise and fall times contribute significantly to CMOS gate performances such as propagation delay or short circuit power dissipation. We present a closed form expression to model output rise and fall times in deep submicron CMOS structures. The model is first developed for inverters considering fast and slow input ramp conditions. It is then extended to gates through a reduction ...

متن کامل

Output transition time modeling of CMOS structures

Non zero signal rise and fall times contribute significantly to CMOS gate performances such as propagation delay or short circuit power dissipation. We present a closed form expression to model output rise and fall times in deep submicron CMOS structures. The model is first developed for inverters considering fast and slow input ramp conditions. It is then extended to gates through a reduction ...

متن کامل

Power-Gating Single-Rail MOS Current-Mode Logic Circuits Using High- Threshold PMOS Transistors as Linear Resistors

Abstract: In this paper, a power-gating technology for single-rail MOS Current Mode Logic (SRMCML) circuits is presented, which use the high-threshold PMOS transistors as linear load resistors to reduce the power dissipation in the sleep mode. The basic SRMCML cells, such as buffer/inverter, AND2/NAND2, AND3/NAND3, OR2/NOR2, OR3/NOR3, XOR2/XNOR2, multiplexer, and 1-bit full adder, are used to v...

متن کامل

Reducing Glitching and Leakage Power in Low Voltage Cmos Circuits

The need for low power dissipation in portable computing and wireless communication is making design communities accept ultra low voltage CMOS processes. With the lowering of' supply voltage, the transistor thresholds (Vth) have to be scaled down to meet the performance requirements. However, such scaling can increase the leakage current through a transistor, thereby increasing the leakage powe...

متن کامل

Flip-Flop Circuit Families:Comparison of Layout and Topology for Low Power VLSI Circuits

The pertinent choice of flip-flop topologies is an essential importance in the design of VLSI integrated circuits for high speed and high performance CMOS circuits. Understanding the suitability of flipflops and selecting the best topology for a given application is an important issueto fulfill the need of the design to satisfy low power and high performance circuit. This paper presents a wides...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2016